ADE9178 datasheet(22/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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Rev. A | 22 of 122

ADC AND HOST SPI

ADC SPI

The ADE9178 receives ADC samples through ADC SPI. The appli-

cation should connect the ADC in daisy-chain mode as explained

in ADE9113 data sheet. The ADC clock should be provided by

crystal to phase A ADC. Clock for phase B, phase C, and phase

N ADC's can be connected to DREADY/CLKOUT of phase A as

shown in Figure 30. The DREADY of last ADC in the chain should

be connected to DREADY input pin of the ADE9178. Figure 30

and Figure 31 show the required connections when four ADCs and

three ADCs are connected to ADE9178, respectively. Single and

two ADC configurations are also supported.

Figure 30. Four ADCs Connection Diagram to ADE9178

Figure 31. Three ADCs Connection Diagram to ADE9178

The ADE9178 supports three voltage (referred as AV, BV, and CV)

and three current channels (referred as AI, BI, and CI) for metrology

measurements and six auxiliary channels (AUX0, AUX1, …, AUX5)

for other measurements. The ADE9178 provides a multiplexer op-

tion that allows any ADC output to be redirected to any processing

datapath by writing appropriate slot number to ADC_REDIRECT0

and ADC_REDIRECT1 register.

In the connections shown in Figure 30 and Figure 31, ADC SPI

frames contain the data in the following sequence as shown in

Table 7 (with last ADC data comes first). This position in SPI frames

is referred as slots in this document where SLOT0 is the I channel

of the ADC, which has its MISO connected directly to ADE9178.

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