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ADPL42002ACPZN1.8-R7 데이터시트(PDF) 15 Page - Analog Devices

부품명 ADPL42002ACPZN1.8-R7
상세설명  20V, 200mA, Low Noise, CMOS LDO Linear Regulator
PDF  22 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADPL42002ACPZN1.8-R7 데이터시트(HTML) 15 Page - Analog Devices

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Data Sheet
ADPL42002
analog.com
Rev. 1
15 of 22
Figure 28. Typical VOUT Response to EN Pin Operation
The upper and lower thresholds are user-programmable and can be set higher than the nominal 1.2V threshold by
using two resistors. The resistance values, REN1 and REN2, can be determined from the following:
REN2 = nominally 10kΩ to 100kΩ
(5)
REN1 = REN2 × (VIN − 1.2V)/1.2V
(6)
Where VIN is the desired turn-on voltage.
The hysteresis voltage increases by the factor (REN1 + REN2)/REN2. For the example shown in Figure 29, the enable
threshold is 3.6V with a hysteresis of 300mV.
Figure 29. Typical EN Pin Voltage Divider
Figure 28 shows the typical hysteresis of the EN pin. This prevents on/off oscillations that can occur due to noise on
the EN pin as it passes through the threshold points.
VEN (V)
1.30
1.25
1.20
1.15
1.10
1.05
0
0.5
1.0
1.5
2.0
2.5
3.5
3.0
–40°C
+25°C
+125°C
VOUT
SENSE/ADJ
VIN
ADPL42002
GND
CIN
2.2µF
COUT
2.2µF
EN
OFF
ON
VIN = 8V
VOUT = 6V
R1
2kΩ
R2
10kΩ
REN1
200kΩ
REN2
100kΩ
SS
CSS
1nF



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