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ADRV9002BBCZ 데이터시트(PDF) 96 Page - Analog Devices

부품명 ADRV9002BBCZ
상세설명  Dual Narrow-Band and Wideband RF Transceiver
PDF  100 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADRV9002BBCZ 데이터시트(HTML) 96 Page - Analog Devices

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Data Sheet
ADRV9002
THEORY OF OPERATION
analog.com
Rev. A | 96 of 100
JTAG BOUNDARY SCAN
The ADRV9002 provides support for a JTAG boundary scan. There
are five dual function pins associated with the JTAG interface.
These pins, as shown in Table 19, are used to access the on-chip
test access port. To enable the JTAG functionality, set the DGPIO_8
pin through DGPIO_11 pin and the MODE pin, as shown in Table
19.
Table 18. Pin Number to AGPIO_xx Mapping and AUXDAC_x
Pin Number
Primary Function
Alternate Function
E12
AGPIO_0
AUXDAC_0
F10
AGPIO_1
AUXDAC_1
E3
AGPIO_2
AUXDAC_2
F5
AGPIO_3
AUXDAC_3
F4
AGPIO_4
Not applicable
G4
AGPIO_5
Not applicable
G6
AGPIO_6
Not applicable
H6
AGPIO_7
Not applicable
G9
AGPIO_8
Not applicable
H9
AGPIO_9
Not applicable
F11
AGPIO_10
Not applicable
G11
AGPIO_11
Not applicable
Table 19. Pin Number to DGPIO_xx Mapping and JTAG Function
Pin Number
Primary Function
JTAG Function, Boundary Scan CMOS Mode
JTAG Function, Boundary Scan LVDS Mode
K6
DGPIO_0
Not applicable
Not applicable
K7
DGPIO_1
Not applicable
Not applicable
K8
DGPIO_2
Not applicable
Not applicable
K9
DGPIO_3
TDO
TDO
K10
DGPIO_4
TRST
TRST
K11
DGPIO_5
TDI
TDI
L4
DGPIO_6
TMS
TMS
L5
DGPIO_7
TCLK
TCLK
L6
DGPIO_8
User sets to 0
User sets to 1
L9
DGPIO_9
User sets to 0
User sets to 0
L10
DGPIO_10
User sets to 0
User sets to 0
L11
DGPIO_11
User sets to 0
User sets to 0
M9
DGPIO_12/TX1_DCLK_OUT−
Not applicable
Not applicable
M10
DGPIO_13/TX1_DCLK_OUT+
Not applicable
Not applicable
M6
DGPIO_14/TX2_DCLK_OUT−
Not applicable
Not applicable
M5
DGPIO_15/TX2_DCLK_OUT+
Not applicable
Not applicable
L13
MODE Pin
User sets to 1
User sets to 1



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