TC9256, 57APG/AFG

2006-07-14

20

Lock Detection Bits

The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit

(unlock bit), which is used to detect, using the reference frequency cycle, the phase difference between the

reference frequency and the divided output of the programmable counter. These systems also have phase error

detection bits (bits PE1to PE3), which are capable of more precise detection (

±0.55 µs to ±7.15 µs).

1.

Unlock Detection Bit (UNLOCK)

This bit detects, using the reference frequency cycle, the phase difference between the reference

frequency and the divided output of the programmable counter. When there is no lock, that is, when the

reference frequency and the divided output of the programmable counter are not the same, unlock F/F is

set.

Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”.

After unlock F/F has been reset in this way, locked state can be detected by checking the unlock detection

bit (UNLOCK) of the output register (D3H). After unlock F/F has been reset, the unlock detection bit must

be checked after a time interval exceeding the reference frequency cycle. This is because the reference

frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct

locked state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This

bit is reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock

detection timing. That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”.

Figure 10