TC9318AFAG datasheet(7/56 Pages) TOSHIBA

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TC9318AFAG/AFBG

2006-07-27

Pin No.

Symbol

Pin Name

Function and Operation

Remarks

VDD

GND

Power-supply pins

Pins to which power is applied.

Normally, VDD = 1.8~3.6 V (3.0 V typ.) is applied.

In back-up mode (when CKSTP instructions are

being executed), voltage can be lowered to 1.0 V.

If voltage falls below 1.5 V while the CPU is

operating, the CPU stops to prevent malfunction

(STOP mode). When the voltage rises above 1.5

V, the CPU restarts.

STOP mode can be detected by checking the

STOP F/F bit. If necessary, execute initialization

or adjust clock by program. When detecting or

preventing CPU malfunctions using an external

circuit, STOP mode can be invalidated and

rendered non-operative by program. In that case,

all four bits of the internal TEST port should be set

to “1”.

If more than 1.8 V is applied when the pin voltage

is 0, the device's system is reset and the program

starts from address “0”. (power on reset)

Note: To operate the power on reset, the power

supply should start up in 10~100 ms.

FMIN

FM programmable

counter input

Programmable counter input pin for FM, VHF

band.

The 1/2

+ pulse swallow system (VHF mode) and

the pulse swallow system (FM mode) are

selectable freely by program.

At the VHF mode, local oscillation output (VCO

output) of 50~230 MHz (0.2Vp-p (min)) is input and

FM mode, 40~130 MHz (0.2Vp-p (min)) is input.

A built-in input amp and C coupling allow

operation at low-level input.

Note: When in the PLL OFF mode or when set to

AMIN input, the input is pulled down.

AMIN

AM local oscillator

signal input

Programmable counter input pin for AM band.

The pulse swallow system (HF mode) and direct

dividing system (LF mode) are freely selectable by

program. At the HF mode, local oscillation output

(VCO output) of 1~45 MHz (0.2 Vp-p (min)) is input

and LF mode, 0.5~12 MHz (0.2 Vp-p (min)) is input.

Built-in input amp operates with low-level input

using a C coupling.

Note: When in PLL OFF mode or when set to

FMIN input, the input is pulled down.

RESET

Reset input

Input pin for system reset signals.

RESET takes place while at low level; at high

level, the program starts from address “0”.

Normally, if more than 1.8 V is supplied to VDD

when the voltage is 0, the system is reset (power

on reset).

Accordingly, this pin should be set to high level

during operation.

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