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FUNCTIONAL BLOCK DIAGRAM

XIN

100Mhz

300Mhz

20Mhz

VSS

VDD

SSCPLL 1

OUT =100Mhz

–0.5%SSC

2-WireSerial

Interface

Control

Logic

LVTTL

Crystal

Oscillator

20Mhz

XOUT

SCLK

SDATA

IREF

IDO

EN

VDD

HCLKout

HCLKout

SSCPLL 2

OUT =200-400Mhz

±1.0%and

±1.5%SSC

150KW

VDD

150KW

CDCDLP223

SCAS836 – DECEMBER 2006

TERMINAL FUNCTIONS

TERMINAL

PIN

TYPE

DESCRIPTION

XIN

1

I

Crystal oscillator input for 20-MHz crystal in parallel resonance

XOUT

2

O

Crystal oscillator output for 20-MHz crystal in parallel resonance

SDATA

9

I/O Open drain

Data I/O, 2-wire serial interface controller, internal 1-M

Ω pullup

SCLK

10

I Interface Clock Clock input, 2-wire serial interface controller, internal 1-M

Ω pullup

20 MHz

5

O LVTTL

Clock output, 20 MHz (buffered output from crystal oscillator)

100 MHz

18

O HCLK

Clock output for XDR clock generator

100 MHz

17

O HCLK

Clock output for XDR clock generator

300 MHz

14

O HCLK

Clock output for DMD system

300 MHz

13

O HCLK

Clock output for DMD system

VDD

4,11,19

Power

3.3 V Power supply

VSS

3,6,12,15,16

Ground

Ground

IREF

20

O RREF to GND IREF pin for HCLK output drive-current biasing

Output enable, 20 MHz, 100 MHz and 200–400 MHz outputs, 150 k

Ω pullup, default =

EN

7

I LVTTL

logic high

Sets 2-wire serial interface ID address bit A0, 150 k

Ω pull-up resistor, default = logic

IDO

8

I LVTTL

high

Table 1. EN Pin (20 MHz, 100 MHz and 300 MHz Clocks)

EN PIN

DESCRIPTION

1

All HCLK outputs, and 20-MHz outputs enabled, detailed device configurations are determined by 2-wire serial interface

settings.

0

All HCLK = true Hi-Z, both PLLs are powered down and 20-MHz output in Hi-Z and Crystal Oscillator disabled, EN overrides

2-wire serial interface settings.

2

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