SM5168 series

SEIKO NPC CORPORATION —2

PINOUT

(Top view)

SM5168A

× series

SM5168C

× series

PIN DESCRIPTION

1

2

8

3

4

6

5

DO

VSS

FIN

OPR

TEST

7

LD

XIN

VDD

1

2

8

3

4

6

5

DO

VSS

FIN

TR

TEST

7

LD

XIN

VDD

Number

Name

I/O

Description

1

VDD

–

2.7 to 3.6V supply

2DO

O

Phase comparator error signal three-state output pin.

Built-in charge pump means that this output can be connected to a low-pass filter. The output

polarity is preset for connection to a passive filter.

3

VSS

–

Ground pin

4

FIN

I

Phase comparator frequency divider (N-counter) signal input pin.

Feedback resistor built-in, so input can be AC-coupled.

5

OPR

(SM5168A

× series)

I

Power-save control pin.

Start when HIGH, standby mode when LOW.

TR

(SM5168C

× series)

Frequency divider switching control.

Switches between 2 sets of reference and comparator frequency dividers.

6

TEST

I

Test pin.

Leave open or connect to VSS for normal operation.

7

LD

O

Unlock signal output pin. (Unlocked when LOW)

8

XIN

I

Reference frequency divider (R-counter) external clock input pin.

Feedback resistor built-in, so input can be AC-coupled.