CDC2510CPWR datasheet(9/18 Pages) TI2

9 / 18 page

CDC2510C

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS621A − DECEMBER 1998 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 9

400

300

250

200

350

105 115 125

150

100

Cycle to Cycle

Peak to Peak

fc − Clock Frequency − MHz

VCC = 3.3 V

C(LY) = C(LF) = 30 pF

TA = 25°C

See Notes A and B

CDC2510C

JITTER

CLOCK FREQUENCY

Figure 10

600

500

400

700

105 115 125

300

200

100

Cycle to Cycle

Peak to Peak

fc − Clock Frequency − MHz

CDC2510A

JITTER

CLOCK FREQUENCY

VCC = 3.3 V

C(LY) = C(LF) = 30 pF

TA = 25°C

See Notes A and B

Figure 11

ANALOG SUPPLY CURRENT

CLOCK FREQUENCY

110

130

150

AVCC = VCC = 3.465 V

Bias = 0/3 V

C(LY) = 30 pf

C(LF) = 0

TA = 25°C

See Notes A and B

fc − Clock Frequency − MHz

Figure 12

SUPPLY CURRENT

CLOCK FREQUENCY

250

150

100

200

110

130

150

fc − Clock Frequency − MHz

300

AVCC = VCC = 3.465 V

Bias = 0/3 V

C(LY) = 30 pf

C(LF) = 0

TA = 25°C

See Notes A and B

NOTES: A. C(LY) = Lumped capacitive load at Y

B. C(LF) = Lumped feedback capacitance at FBIN

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