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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MSC8144EC 데이터시트(PDF) 39 Page - Freescale Semiconductor, Inc |
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MSC8144EC 데이터시트(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 80 page  Electrical Characteristics MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6 Freescale Semiconductor 39 Table 26 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.8 V. Table 27 provides the input AC timing specifications for the DDR SDRAM interface. 2.7.4.2 DDR SDRAM Output AC Timing Specifications Table 28 provides the output AC timing specifications for the DDR SDRAM interface. AC input high voltage VIH MVREF + 0.31 — V Note: At recommended operating conditions with VDDDDR of 2.5 ± 5%. Table 26. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Parameter Symbol Min Max Unit AC input low voltage VIL —MVREF – 0.25 V AC input high voltage VIH MVREF + 0.25 — V Note: At recommended operating conditions with VDDDDR of 1.8 ± 5%. Table 27. DDR SDRAM Input AC Timing Specifications Parameter Symbol Min Max Unit Controller Skew for MDQS—MDQ/MECC/MDM1 •400 MHz •333 MHz •266 MHz •200 MHz tCISKEW –365 –390 –428 –490 365 390 428 490 ps ps ps ps Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is captured with MDQS[n]. Subtract this value from the total timing budget. 2. At recommended operating conditions with VDDDDR (1.8 V or 2.5 V) ± 5% Table 28. DDR SDRAM Output AC Timing Specifications Parameter Symbol 1 Min Max Unit MCK[n] cycle time, (MCK[n]/MCK[n] crossing)2 tMCK 310 ns ADDR/CMD output setup with respect to MCK3 •400 MHz •333 MHz •266 MHz •200 MHz tDDKHAS 1.95 2.40 3.15 4.20 — — — — ns ns ns ns ADDR/CMD output hold with respect to MCK3 •400 MHz •333 MHz •266 MHz •200 MHz tDDKHAX 1.95 2.40 3.15 4.20 — — — — ns ns ns ns MCSn output setup with respect to MCK3 •400 MHz •333 MHz •266 MHz •200 MHz tDDKHCS 1.95 2.40 3.15 4.20 — — — — ns ns ns ns MCSn output hold with respect to MCK3 •400 MHz •333 MHz •266 MHz •200 MHz tDDKHCX 1.95 2.40 3.15 4.20 — — — — ns ns ns ns MCK to MDQS Skew4 tDDKHMH –0.6 0.6 ns Table 25. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface (continued) Parameter Symbol Min Max Unit |
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