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RISE TIME (ps)

CLC006

www.ti.com

SNLS015G – AUGUST 1998 – REVISED APRIL 2013

OUTPUT RISE AND FALL TIMES

Output load capacitance can significantly affect output rise and fall times. The effect of load capacitance, stray or

otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing

all interconnecting trace lengths. Figure 15 shows the effect on risetime of parallel load capacitance across a

150

Ω load.

Figure 15. Rise Time vs CL

PCB Layout Recommendations

Printed circuit board layout affects the performance of the CLC006. The following guidelines will aid in achieving

satisfactory device performance.

•

Use a ground plane or power/ground plane sandwich design for optimum performance.

•

Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum

electrolytic capacitor located no more than 0.1” (2.5 mm) from the device power pins.

•

Provide short, symmetrical ground return paths for:

–

inputs,

–

supply bypass capacitors and

–

the output load.

•

Provide short, grounded guard traces located

–

under the centerline of the package,

–

0.1” (2.5 mm) from the package pins

–

on both top and bottom of the board with connecting vias.

Copyright © 1998–2013, Texas Instruments Incorporated

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