LM2512A

SNLS269B – AUGUST 2007 – REVISED MAY 2013

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ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

IDD

Total Supply Current -

MC = 80 MHz,

VDDIO

0.02

0.07

mA

Enabled(3)

Checkerboard Pattern

VDD/VDDA

5.4

9.0

mA

3 MD Lane(4)

MC = 60 MHz,

VDDIO

0.01

mA

Checkerboard Pattern

VDD/VDDA

4.1

mA

2 MD Lane

Supply Current -Enabled

MC = 60 MHz,

VDDIO

0.02

mA

Pseudo-Random

VDD/VDDA

Pattern

3.7

mA

2 MD Lane

IDDZ

Supply Current—Disable

PD* = L

VDDIO

<1

2

µA

Power Down Modes

VDD/VDDA

<1

5

µA

Ta = 25°C

Stop Clock

VDDIO

<1

2

µA

VDD/VDDA

<1

5

µA

(3)

For IDD tests - input signal conditions are: (swing, edge, freq, DE = H, VS = L, HS = L, RGB Checkerboard Pattern: AAAAAA-555555)

(4)

Total Supply Current Conditions: checkerboard data pattern, 20MHz PCLK (3MDs), TYP VDDIO = VDDA = VDD = 1.8V, MAX VDDIO =

3.0V, MAX VDDA = VDD = 2.0V.

SWITCHING CHARACTERISTICS

Over recommended operating supply and temperature ranges unless otherwise specified.

(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

PARALLEL BUS TIMING

tSET

Set Up Time

SER Inputs Figure 1

5

ns

tHOLD

Hold Time

5

ns

SERIAL BUS TIMING

tDVBC

Serial Data Valid before Clock

SER Data Pulse Width Figure 2, (2) (3)

0.38

UI

Edge

tDVAC

Serial Data Valid after Clock

0.38

UI

Edge

POWER UP TIMING

t0

Bias Up Time

See Figure 9

PCLK

200

cycles

t1

MC Pulse Width LOW

PCLK

200

cycles

t2

MC Pulse Width HIGH

PCLK

20

cycles

t3

MC Pulse LOW

PCLK

8

cycles

t4

MC Pulse LOW - SER PLL

PCLK

600

Lock Counter

cycles

tPZXclk

Enable Time - Clock Start

PCLK to MCOUT Figure 4

See(4)

MPL POWER OFF TIMING

tPAZ

Disable Time to Power Down

See(5)

15

ms

tPXZclk

Disable Time - Clock Stop

PCLK to MCOUT Figure 3

PCLK

2

cycles

SPI INTERFACE

(1)

Typical values are given for VDDIO = 1.8V and VDD = VDDA = 1.8V and TA = 25°C.

(2)

1 UI is the serial data MD pulse width = 1 / 8xPCLK (3 MD lanes), 1 UI is the serial data MD pulse width = 1 / 12xPCLK (2 MD lanes)

(3)

This is a functional parameter and is specified by design or characterization.

(4)

Enable Time is a complete MPL start up comprised of t0 + t1 + t2 + t3 + t4.

(5)

Specified functionally by the IDDZ parameter. See also Figure 10.

4

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