LM48520, LM48520TLBD

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SNAS367C – FEBRUARY 2008 – REVISED APRIL 2013

Maximum Switch Current

The maximum FET switch current available before the current limiter cuts in is dependent on duty cycle of the

application. This is illustrated in a graph in the Typical Performance Characteristics section which shows typical

values of switch current as a function of effective (actual) duty cycle.

Calculating Output Current of Boost Converter (IAMP)

The load current is related to the average inductor current by the relation:

ILOAD = IIND(AVG) x (1 - DC)

(8)

where:

"DC" is the duty cycle of the application

The switch current can be found by:

ISW = IIND(AVG) + 1/2 (IRIPPLE)

(9)

Inductor ripple current is dependent on inductance, duty cycle, input voltage and frequency:

IRIPPLE = DC x (VIN-VSW) / (f x L)

(10)

combining all terms, we can develop an expression which allows the maximum available load current to be

calculated:

ILOAD(max) = (1–DC)x(ISW(max)–DC(VIN-VSW))/fL

(11)

The equation shown to calculate maximum load current takes into account the losses in the inductor or turn-OFF

switching losses of the FET and diode.

Design Parameters VSW and ISW

The value of the FET "ON" voltage (referred to as VSW in Equation 4 thru Equation 9) is dependent on load

current. A good approximation can be obtained by multiplying the "ON Resistance" of the FET times the average

inductor current.

FET on resistance increases at VIN values below 5V, since the internal N-FET has less gate voltage in this input

voltage range (see Typical Performance Characteristics curves). Above VIN = 5V, the FET gate voltage is

internally clamped to 5V.

The maximum peak switch current the device can deliver is dependent on duty cycle. For higher duty cycles, see

Typical Performance Characteristics curves.

Inductor Suppliers

The recommended inductor for the LM48520 is the NR8040T6R8N from Taiyo Yuden. When selecting an

inductor, make certain that the continuous current rating is high enough to avoid saturation at peak currents,

where:

IIND = (PV1 / VDD) x ILOAD(BOOST)

(12)

A suitable core type must be used to minimize core (switching) losses, and wire power losses must be

considered when selecting the current rating.

PCB Layout Guidelines

High frequency boost converters require very careful layout of components in order to get stable operation and

low noise.

All components must be as close as possible to the LM48520 device. It is recommended that a four layer PCB

be used so that internal ground planes are available.

Some additional guidelines to be observed (all designators are referencing Figure 1):

1. Keep the path between L1, D1, and Co extremely short. Parasitic trace inductance in series with D1 and Co

will increase noise and ringing.

2. The feedback components R1, R2 and Cf1 must be kept close to the FB pin to prevent noise injection on the

FB pin trace.

3. Since the external components of the boost converter are switching, L1 and D1 should be kept away from

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