GND

+

-

5 P$

40 k:

Rectified AC

BIAS

AC

AC

LM3450/50A

Sample

CHLD

CSEN

RSEN

RHLD

QPS

RBS

+

-

VSEN

ISEN

HOLD

10k

NTC

15k

3904

Connect if thermal

protection circuit is

not desired

QPS

thermal

protection

circuit

0.0

0.2

0.4

0.6

0.8

1.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

LM3450/A DEMODULATED VAC PIN DUTY CYCLE

1V

0.5V

2V

2.5V

1.5V

VADJ=3V

LM3450

www.ti.com

SNVS681D – NOVEMBER 2010 – REVISED MAY 2013

Figure 30. Complete Decoder Mapping

Since the buffered decoder output has amplitude equal to VADJ and the resulting PWM signal is filtered into an

analog voltage at FLT2, the VADJ pin can be used to change the mapping as shown in Figure 30. The maximum

LED current (DIM = 0) when VADJ = 3V corresponds to decoded angles of 70% or greater. Some dimmers have a

maximum angle greater than this. If VADJ is reduced to 2.5V, the maximum LED current will correspond to an

angle of 80% and at VADJ = 2V the maximum will occur at a decoded angle of 95%.

The VADJ pin can also be used to implement a standard analog adjust function. If the demodulated phase angle

at VAC is above 85%, then the fast filter is always enabled (500kΩ shorted) and the VADJ pin can solely be used

to scale the DIM pin duty cycle. When VADJ is pulled below 75mV the part enters low power shutdown so the

maximum attainable contrast ratio using VADJ only is approximately 40:1.

Both FLT1 and FLT2 have pull-down MosFETs that are turned on when VCC UVLO falling threshold is triggered.

This provides a quick discharge path for the capacitors and eliminates the possibility of an undesired light level at

the next startup.

Figure 31. Dynamic Hold Circuit

Copyright © 2010–2013, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: LM3450