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74ACT125B 데이터시트(PDF) 1 Page - STMicroelectronics |
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74ACT125B 데이터시트(HTML) 1 Page - STMicroelectronics |
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1 / 8 page ![]() 74ACT125 QUAD BUS BUFFERS (3-STATE) PRELIMINARY DATA May 1997 PIN CONNECTION AND IEC LOGIC SYMBOLS s HIGH SPEED: tPD = 6.5 ns (TYP.) at VCC =5V s LOW POWER DISSIPATION: ICC =8 µA (MAX.) at TA =25 oC s COMPATIBLE WITH TTL OUTPUTS VIH =2V (MIN), VIL = 0.8V (MAX) s 50 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|= IOL =24 mA (MIN) s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 4.5V to 5.5V s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 125 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The ACT125 is an high-speed CMOS QUAD BUS BUFFERS fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power applications maintaining high speed operation similar to equivalent Bipolar Schottky TTL. These devices require the same 3-STATE control input G to be taken high to make the output go in to the high impedance state. The device is designed to interface directly High Speed CMOS systems with TTL, NMOS and CMOS output voltage levels. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ORDER CODES : 74ACT125B 74ACT125M M (Micro Package) B (Plastic Package) 1/8 |
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