LOW IMPEDANCE

VOLTAGE REFERENCE

VI

RG1

RG2

VOCM

RF1

RF2

EN

A/D

RISO1

CS

8-18 pF

+

-

a

VREF

RISO2

RG

RG

VOCM

RL

VO

RF

RF

CL

RO

RO

EN

+

-

VI

a

VO1

VO2

VI2

VI1

RM

RT

RS

VICM = VOCM

VICM =

VI1 + VI2

2

*VCM =

VO1 + VO2

2

*BY DESIGN

LMP8350

SNOSB80C – FEBRUARY 2011 – REVISED OCTOBER 2015

www.ti.com

Application Information (continued)

Figure 32. AC Coupled for Single-Supply Operation

8.1.3 Driving Analog to Digital Converters

Analog to digital converters (ADC) present challenging load conditions. They typically have high impedance

inputs with large and often variable capacitive components. As well, there are usually current spikes associated

with switched capacitor or sample and hold circuits. Figure 33 shows a typical circuit for driving an ADC. The two

resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In addition, the

resistors form part of a lowpass filter which helps to provide anti alias and noise reduction functions. The CS

capacitor helps to smooth the current spikes associated with the internal switching circuits of the ADC and also

are a key component in the lowpass filtering of the ADC input. The capacitor should be a low distortion capacitor,

such as an NPO, to avoid causing significant distortion terms. In the circuit of Figure 33, the cutoff frequency of

the filter is calculated by Equation 3. This should be slightly less than the sampling frequency.

1 / (2 ×

π × (RISO1 + RISO2) × (CS + CCONVERTER))

(3)

NOTE

The ADC input capacitance must be factored into the frequency response of the input

filter. Also as shown in Figure 33, the input capacitance to many ADCs is variable based

on the clock cycle. For lower-speed, precision ADC's, the external cap is generally sized

to ten times the internal sampling capacitor value. See the data sheet for your particular

ADC for details.

Figure 33. Driving an ADC

24

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