AD7984

Rev. 0 | Page 19 of 24

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7984s are connected

to an SPI-compatible digital host.

A connection diagram example using two AD7984s is shown in

Figure 32, and the corresponding timing is given in Figure 33.

With SDI high, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase and

the subsequent data readback (if SDI and CNV are low, SDO is

driven low). Prior to the minimum conversion time, SDI can be

used to select other SPI devices, such as analog multiplexers,

but SDI must be returned high before the minimum conversion

time elapses and then held high for the maximum possible

conversion time to avoid the generation of the busy signal

indicator. When the conversion is complete, the AD7984

enters the acquisition phase and goes into standby mode. Each

ADC result can be read by bringing its SDI input low, which

consequently outputs the MSB onto SDO. The remaining data

bits are then clocked by subsequent SCK falling edges. The data

is valid on both SCK edges. Although the rising edge can be

used to capture the data, a digital host using the SCK falling

edge allows a faster reading rate, provided it has an acceptable

high (whichever occurs first), SDO returns to high impedance

and another AD7984 can be read.

AD7984

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

CS1

CS2

AD7984

SDI

SDO

CNV

SCK

Figure 32. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

SDO

D17

D16

D15

D1

D0

SCK

12

3

34

35

36

CONVERSION

ACQUISITION

ACQUISITION

SDI(CS1)

CNV

D1

16

17

D0

D17

D16

19

20

18

SDI(CS2)

Figure 33. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing