LP5520TLSLASHNOPB.A datasheet(14/45 Pages) TI2

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ROUT

GOUT

BOUT

PWMR

PWMG

PWMB

10 ms/100 Hz

3.333 ms

Dead time

Internal PWM cycle

ROUT

GOUT

BOUT

50%

100%

819 Ps/1.22 kHz in normal PWM

52 Ps/19.2 kHz in fast PWM

LP5520

SNVS440B – MAY 2007 – REVISED MARCH 2016

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Figure 17. Pulse Positions in the PWM Cycle

7.3.2.4 Sequential Mode

Completely non-overlapping timing can be obtained by using the sequential mode as shown in Figure 18. The

timing is defined with external PWM control inputs. The minimum trigger pulse width in the PWM inputs is 1 µs.

There is no limitation on the maximum width of the pulse as long as it is shorter than the whole sequence.

Figure 18. Non-Overlapping External Synchronized Sequential Mode

In sequential mode the PWM cycle is synchronized to trigger pulses and the amount of PWM pulses per trigger

can be defined to 2, 3 or 4 using the <seq_mode0> and <seq_mode1> control bits. This makes possible to use

sequence lengths of about 5 ms, 7.5 ms or 10 ms. Fast PWM can be used in sequential mode, but the frame

timing is as with normal PWM.

The PWM timing and synchronization timing originate from different clock sources. Some margin must be

allowed for clock tolerances. This margin shows as a dead time in the waveform graph. Some dead time must be

allowed so that no PWM pulse is clipped. Clipping would distort the intensity balance between the LEDs. The

dead time causes some intensity reduction, but assures the current balance.

PWM mode is defined by <seq_mode1> and <seq_mode2> control bits of rgb_control (00H) register:

LP5520TL/NOPB.A 데이터시트(PDF) 14 Page - Texas Instruments