LAN9252VSLASHML datasheet(210/329 Pages) MICROCHIP

210 / 329 page

LAN9252

DS00001909A-page 210

 2015 Microchip Technology Inc.

12.11.2

ETHERCAT CSR WRITES

To perform a write to an individual EtherCAT Core register, the desired data must first be written into the EtherCAT CSR

Interface Data Register (ECAT_CSR_DATA). Valid data is always aligned into the lowest bits of the EtherCAT CSR Inter-

face Data Register (ECAT_CSR_DATA).

The write cycle is initiated by performing a single write to the EtherCAT CSR Interface Command Register (ECAT_CS-

R_CMD) with the CSR Busy (CSR_BUSY) bit set, the CSR Address (CSR_ADDR) field set to the desired register

address, the Read/Write (R_nW) bit cleared and the CSR Size (CSR_SIZE) field set to the desired size. The completion

of the write cycle is indicated by the clearing of the CSR Busy (CSR_BUSY) bit.

Figure 12-11 illustrates the process required to perform a EtherCAT Core CSR write. Minimum wait periods are required

where noted. Minimum wait periods are required where noted. The minimum wait periods as specified in Table 5-2,

“Read After Write Timing Rules,” on page 35 are required where noted.

12.11.3

ETHERCAT PROCESS RAM READS

Process data is transferred from the EtherCAT Core through a 16 deep 32-bit wide FIFO. The FIFO has the base

address of 00h, however, it is also accessible at seven additional contiguous memory locations. The Host may access

the FIFO at any of these alias port locations, as they all function identically and contain the same data. This alias port

addressing is implemented to allow hosts to burst through sequential addresses.

For HBI access, the Process RAM Read Data FIFO may also be accessed using FIFO Direct Selection mode. In this

mode, the address input is ignored and all read accesses are directed to the Process RAM Read Data FIFO. See Sec-

tion 9.4.3.1, "FIFO Direct Select Access," on page 68.

FIGURE 12-11:

ETHERCAT CSR WRITE ACCESS FLOW DIAGRAM

Idle

Write Data

Write

Command

Read

Command

CSR_ BUSY = 0

CSR Write

CSR_ BUSY =1

min wait period

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