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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN9252V/ML 데이터시트(PDF) 213 Page - Microchip Technology |
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LAN9252V/ML 데이터시트(HTML) 213 Page - Microchip Technology |
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213 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 213 LAN9252 Based on the starting address and length, the valid bytes in the last FIFO write are as follows: If the initial length is 4 bytes of less and all bytes fit into one write, the valid bytes in the only FIFO write are as follows: 12.11.4.1 Aborting a Write If necessary, a write command can be aborted by setting the PRAM Write Abort (PRAM_WRITE_ABORT) bit in the Eth- erCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD). 12.12 EtherCAT Reset After writing 0x52 (R), 0x45 (E) and 0x53 (S) into the ESC Reset ECAT Register with 3 consecutive frames or after writ- ing 0x52 (R), 0x45 (E) and 0x53 (S) into the ESC Reset PDI Register with 3 consecutive writes, a device reset (and optional system reset) will occur, as defined in Section 6.2.1.3, "EtherCAT System Reset," on page 40. TABLE 12-10: ETHERCAT PROCESS RAM VALID FIRST WRITE BYTES Starting Address[1:0] 00b bytes 3, 2, 1 and 0 01b bytes 3, 2 and 1 10b bytes 3 and 2 11b byte 3 TABLE 12-11: ETHERCAT PROCESS RAM VALID LAST WRITE BYTES Starting Length[1:0] Starting address[1:0] 01b (e.g. 5, 9, etc.) 10b (e.g. 6, 10, etc.) 11b (e.g. 7, 11, etc.) 00b (e.g. 8, 12, etc.) 00b byte 0 bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 01b bytes 1 and 0 bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 10b bytes 2, 1 and 0 bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 11b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 TABLE 12-12: ETHERCAT PROCESS RAM VALID BYTES ONE WRITE Starting Length starting address[1:0] 4123 00b bytes 3, 2, 1 and 0 byte 0 bytes 1 and 0 bytes 2, 1 and 0 01b na byte 1 bytes 2 and 1 bytes 3, 2 and 1 10b na byte 2 bytes 3 and 2 na 11b nabyte 3na na Note: It is likely that the last frame of the sequence will not return to the master (depending on the topology), because the links to and from the slave which is reset will go down. |
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