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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LAN9252V/ML 데이터시트(PDF) 216 Page - Microchip Technology |
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LAN9252V/ML 데이터시트(HTML) 216 Page - Microchip Technology |
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216 / 329 page  LAN9252 DS00001909A-page 216 2015 Microchip Technology Inc. 12.13.2 ETHERCAT PROCESS RAM WRITE DATA FIFO (ECAT_PRAM_WR_DATA) This write only register is used in conjunction with the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD) and the EtherCAT Process RAM Write Address and Length Register (ECAT_PRAM_WR_ADDR_LEN) to perform write operations to the EtherCAT Core Process RAM. The host should not write this register unless there is available space as indicated by the PRAM Write Space Available (PRAM_WRITE_AVAIL) bit in the EtherCAT Process RAM Write Command Register (ECAT_PRAM_WR_CMD). Offset: 020h-03Ch Size: 32 bits Bits Description Type Default 31:0 EtherCAT Process RAM Write Data (PRAM_WR_DATA) This field contains the value written to the EtherCAT Core Process RAM. Note: Some bytes maybe invalid based on the starting address and transfer length. WO - |
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