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TUSB2136 데이터시트(PDF) 12 Page - Texas Instruments

부품명 TUSB2136
상세설명  Universal Serial Bus Compound Hub with General Purpose 8052 MCU
PDF  53 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

TUSB2136 데이터시트(HTML) 12 Page - Texas Instruments

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1−5
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
VCC
10,39,62
Power supply input, 3.3 V typical
VDD18†
37
1.8 V. When VREN is low, 1.8 V must be applied to provide current for the core during suspend.
VREN
38
I
Voltage regulator enable: enable active LOW; disable active HIGH
X2
60
O
12-MHz crystal output
X1
61
I
12-MHz crystal input
† During normal operation, the internal 3.3- to 1.8-V voltage regulator of the TUSB2136 is enabled and provides power to the core. To save power
during the suspend mode, the internal regulator is disabled. In this case, the pin becomes an input, and a simple external power source is required
to provide power to the core. This source needs to supply a very limited amount of power (10
µA maximum) within the voltage range of 1 V to
1.95 V.
NOTE 1: The MCU treats the outputs as open-drain types in that the output can be driven low continuously, but a high output is driven for two
clock cycles and then the output is placed in a high-impedance state.
TEST0
TEST1
FUNCTION
0
0
Selects 48-MHz clock input (from an oscillator or other onboard clock source)
0
1
Reserved for testing purposes
1
0
Reserved for testing purposes
1
1
Selects 12-MHz crystal as clock source (default)
1.6
Revision History
Version
Date
Changes
Dec−2000
Initial Release
A
Feb−2001
1.
Clarified pin descriptions for P3.2 (56), P3.3 (55), and VDDOUT (37).
2.
Add red/write capability for each of the register bits.
3.
Corrected Quiescent and Suspend current figures in Table 3.3.
4.
Added Section 4.2 Reset Timing
5.
Added NOTE to cover page.
B
Jun−2002
1.
Changed name of pin 37 from VDDOUT to VDD18 and enhanced pin description.
2.
Removed NOTE from cover page.
C
Apr−2003
1.
Simplified Terminal Function Table for GPIO Ports
2.
Clarified GPIO Port 3 pin descriptions in Terminal Function Table
3.
Clarified functional description for Pins S2 and S3 (8 & 9)
4.
Clarified TEST0 & TEST1 (14 & 15) pin functions in Terminal Functions Table
5.
Added note on open-drain output pins for Terminal Functions Table
6.
Added additional note for operation of VDD18 (pin 37) to Terminal Functions Table.
7.
Removed most references to ROM version including Fig 2.2.
8.
Added USB Logo to Cover page



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