SN74F175

QUADRUPLE D-TYPE FLIP-FLOP

WITH CLEAR

SDFS058B – D293, MARCH 1987 – REVISED MAY 2002

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Contains Four Flip-Flops With Double-Rail

Outputs

D Buffered Clock and Direct Clear Inputs

D Applications Include:

– Buffer/Storage Registers

– Shift Registers

– Pattern Generators

description

This positive-edge-triggered flip-flop utilizes TTL

circuitry to implement D-type flip-flop logic with a

direct clear (CLR) input. Information at the data

(D) inputs meeting setup-time requirements is

transferred to outputs on the positive-going edge

of the clock pulse. Clock triggering occurs at a

particular voltage level and is not directly related

to the transition time of the positive-going pulse.

When the clock (CLK) input is at either the high or

low level, the D-input signal has no effect at the

output.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N

Tube

SN74F175N

SN74F175N

0

°Cto70°C

SOIC

D

Tube

SN74F175D

F175

0

°C to 70°C

SOIC – D

Tape and reel

SN74F175DR

F175

SOP – NS

Tape and reel

SN74F175NSR

74F175

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

INPUTS

OUTPUTS

CLR

CLK

D

Q

Q

L

X

X

L

H

H

↑

HH

L

H

↑

LL

H

H

L

X

Q0

Q0

D, N, OR NS PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLR

1Q

1Q

1D

2D

2Q

2Q

GND

VCC

4Q

4Q

4D

3D

3Q

3Q

CLK

Copyright

 2002, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.