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2

Revision 1.0

Features

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Docking LPC Switch

— Hot plugability

— LPCPD and CLKRUN support

— The connection is controlled by software

— Low switch resistance and propagation delay

— Programmable Clock to Reset Delay

— Software compatible with the 16550A and the 16450

— Shadow register support for write-only bit monitoring

— FIR IrDA 1.1 compliant

— HP-SIR

— ASK-IR option of SHARP-IR

— DASK-IR option of SHARP-IR

— Consumer Remote Control supports RC-5, RC-6,

NEC, RCA and RECS 80

— DMA support: one or two channels

— Software compatible with the 16550A and the 16450

— Shadow register support for write-only bit monitoring

— UART data rates up to 1.5 Mbaud

— Supports IRQ assertion

— Programmable drive type for each output pin (open-

drain, push-pull or output disable)

— Programmable option for internal pull-up resistor on

each input pin

— Output lock option

— Input debounce mechanism

— 8-bit I/O cycles

— LPCPD and CLKRUN support

— Implements PCI mobile design guide recommenda-

tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998)

— PnP Configuration Register structure

— Flexible resource allocation for all logical devices

selected from four possible DMA channels

— 14.318 MHz or 48 MHz clock input

— LPC clock, 0 or 30 MHz to 33 MHz

— 14.318 MHz or 48 MHz clock output to the docking

station

— Base Address (BADDR) strap to determine the base

address of the Index-Data register pair

— Docking LPC disable (DLPC_DIS) strap to control

the LPC-to-LPC Switch

— Strap Inputs to select testability mode

— 3.3V supply operation

— All pins are 5V tolerant, except LPC bus pins

— All pins are back-drive protected, except LPC bus pins

— XOR Tree

— TRI-STATE device pins

Internal Block Diagram

FIR Port

Bus

Interface

LPC Interface

I/O

Serial Port

Serial

Interface

GPIO Ports

Ports

Docking

LPC Switch

Docking LPC

Interface

14.31818 MHz

Clock

Generator

48 MHz

FIR

Interface