0.1 F

5V

VCC

GND

Control

Phase detector

CLR

A

B

Q

C

D

Oscillator

1024

976Hz

1MHz

CLK

TP

16

Z>^294

SN74LS292, SN74LS294

www.ti.com

SDLS153A – JANUARY 1981 – REVISED JANUARY 2016

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

This device is used for configurable frequency, programmable frequency, and timing division as shown in Typical

Application.

9.2 Typical Application

Figure 10. Typical application

9.2.1 Design Requirements

This device does not have balanced output drive. Take care to avoid bus contention because it can sink currents

that would exceed maximum limits. The high drive will also create fast edges into light loads so routing and load

conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

1. Recommended Input Conditions:

–

Rise time and fall time specs. See (

Δt/ΔV) in Recommended Operating Conditions.

–

Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.

–

Inputs can go as high as (VI max) in Recommended Operating Conditions at any valid VCC.

2. Recommended Output Conditions:

–

Load currents should not exceed (IOH,IOL) per output. These limits are located in the Recommended

Operating Conditions.

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