STM32F427NET7TR datasheet(24/231 Pages) STMICROELECTRONICS

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Functional overview

STM32F427xx STM32F429xx

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detected, the system automatically switches back to the internal RC oscillator and a

software interrupt is generated (if enabled). This clock source is input to a PLL thus allowing

to increase the frequency up to 180 MHz. Similarly, full interrupt management of the PLL

clock entry is available when necessary (for example if an indirectly used external oscillator

fails).

Several prescalers allow the configuration of the two AHB buses, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB

buses is 180 MHz while the maximum frequency of the high-speed APB domains is

90 MHz. The maximum allowed frequency of the low-speed APB domain is 45 MHz.

The devices embed a dedicated PLL (PLLI2S) and PLLSAI which allows to achieve audio

class performance. In this case, the I2S master clock can generate all standard sampling

frequencies from 8 kHz to 192 kHz.

3.15

Boot modes

At startup, boot pins are used to select one out of three boot options:

•

Boot from user Flash

•

Boot from system memory

•

Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory

through a serial interface. Refer to application note AN2606 for details.

3.16

Power supply schemes

•

VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when

enabled), provided externally through VDD pins.

•

VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

•

VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and

backup registers (through power switch) when VDD is not present.

Note:

VDD/VDDA minimum value of 1.7 V is obtained with the use of an external power supply

supervisor (refer to Section 3.17.2: Internal reset OFF). Refer to Table 3: Voltage regulator

configuration mode versus device operating mode to identify the packages supporting this

option.

3.17

Power supply supervisor

3.17.1

Internal reset ON

On packages embedding the PDR_ON pin, the power supply supervisor is enabled by

holding PDR_ON high. On the other package, the power supply supervisor is always

enabled.

The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and

ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is

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