THS12082CDAR datasheet(7/44 Pages) TI2

7 / 44 page

THS12082

12-BIT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTERS

SLAS271B – MAY 2000 – REVISED DECEMBER 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing specifications (AVDD = BVDD = DVDD = 5 V, VREFP = 3.5 V, VREFM = 1.5 V, CL < 30 pF )†

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(DATA_AV)

Delay time

td(o)

Delay time

td(pipe)

Latency

CONV

CLK

† Refer to Figure 2

timing specification of the single conversion mode‡

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Clock cycle of the internal clock oscillator

117

125

133

Pulse duration CONVST

1 analog input

1.5

×tc

Pulse duration, CONVST

2 analog inputs

2.5

×tc

tdA

Aperture time

Time between consecutive start of single

1 analog input

×tc

conversion

2 analog inputs

×tc

1 analog input, TL = 1

6.5

×tc+15

2 analog inputs, TL = 2

7.5

×tc+15

1 analog input, TL = 4

×t2 +6.5×tc+15

td(DATA AV)

Delay time, DATA_AV becomes active for the

2 analog inputs, TL = 4

t2 +7.5×tc+15

td(DATA_AV)

trigger level condition: TRIG0 = 1, TRIG1 = 1

1 analog input, TL = 8

×t2 +6.5×tc+15

2 analog inputs, TL = 8

×t2 +7.5×tc+15

1 analog input, TL = 14

×t2 +6.5×tc+15

2 analog inputs, TL = 12

×t2 +7.5×tc+15

‡ Refer to Figure 1

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