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XC910C001FASL 데이터시트(PDF) 13 Page - Torex Semiconductor |
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XC910C001FASL 데이터시트(HTML) 13 Page - Torex Semiconductor |
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13 / 22 page ![]() 13/22 XC9101 Series ● Instruction on Pattern Layout ① In order to stablize VDD's voltage level, we recommend that a by-pass capacitor (CDD) be connected as close as possible to the VIN & VSS pins. ② In order to stablize the GND voltage level which can fluctuate as a result of switching, we suggest that C_CLK's, R_CLK's & C_GAIN's GND be separated from Power GND and connected as close as possible to the VSS pin (by-pass capacitor, CDD). Please use a multi layer board and check the wiring carefully. < XC9101D Series Pattern Layout Examples> 2 Layer Evaluation Board ■ NOTES ON USE (Continued) Power GND IC GND VDD Line Through Hole RFB1 RFB2 CFB CL C_GAIN R_CLK C_CLK CDD L N-MOS RSEN SD VIN CIN C_SS R_SS 1 2 3 4 Through Hole 5 6 7 8 R_CLK, C_CLK, C_GAIN, RFB2 GND 1 2 3 4 5 6 7 85 6 7 8 5 6 7 8 |
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