SLAS367 datasheet(19/56 Pages) TI2

19 / 56 page

3–7

FS is output for initial 132 MCLK and it must be kept low. DSP needs to keep FS low or 3-state for this period to avoid

contention on FS.

3.6.7

Asynchronous Sampling

(Codecs in cascade are sampled at different sampling frequency)

The AIC15s SMARTDM support different sampling frequency between the different codecs in cascade connecting

to a single serial port. In this case, all codecs are required to sample at the same frequency that is the frequency of

the FS signal. Then the desired sampling frequency of each codec is calculated by D2–D0 of control register 3.

Example: fs1 and fs2 are desired sampling rates for CODEC1 and CODEC2 respectively:

FS = MCLK/(16xMxNxP)

FS = n1 x fs1 (n1 = 1,2, 0, 8 defined in the control register 3 of CODEC1)

FS = n2 x fs2 (n2 = 1,2, 0, 8 defined in the control register 3 of CODEC2)

For validating the conversion data from this operation:

For DAC: DSP need to give same data for n1 samples. CODEC1 picks one of n1 samples.

For ADC: CODEC1 gives same data for n1 samples. DSP should pick one of n1 samples.

SCLK

FSD

(Output)

DIN/DOUT

(16 Bit)

MSB

LSB

D15

D14

16 SCLKs

Figure 3–6. Timing Diagram for FSD Output

MCLK

DIN

DOUT

SCLK

MCLK

DIN

DOUT

SCLK

MCLK

DIN

DOUT

SCLK

Slave 2

Slave 1

Slave 0

Master

MCLK

DIN

DOUT

FSD

SCLK

FSD

CLKOUT

FSX

FSR

CLKX

CLKR

TMS320C5x

M/S

FSD

IOVDD

1 k

Ω

100 MHz Max

IOVDD

Figure 3–7. Cascade Connection (To DSP Interface)

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