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74VHCT132AM 데이터시트(PDF) 1 Page - STMicroelectronics

부품명 74VHCT132AM
상세설명  QUAD 2-INPUT SCHMITT NAND GATE
PDF  7 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

74VHCT132AM 데이터시트(HTML) 1 Page - STMicroelectronics

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74VHCT132A
QUAD 2-INPUT SCHMITT NAND GATE
PRELIMINARY DATA
February 2000
s
HIGH SPEED: tPD = 6.5 ns (TYP.) at VCC =5V
s
LOW POWER DISSIPATION:
ICC =2
µA (MAX.) at TA =25 oC
s
TYPICAL HYSTERESIS: 0.7V at VCC = 4.5V
s
POWER DOWN PROTECTION ON INPUTS &
OUTPUTS
s
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 8 mA (MIN)
s
BALANCED PROPAGATION DELAYS:
tPLH
≅ tPHL
s
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 132
s
IMPROVED LATCH-UP IMMUNITY
s
LOW NOISE: VOLP = 0.8V (Max.)
DESCRIPTION
The 74VHCT132A is an advanced high-speed
CMOS QUAD 2-INPUT SCHMITT NAND GATE
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2MOS technology.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
Pin configuration and function are the same as
those of the VHCT00A but the VHCT132A has
hysteresis.
This together with its schmitt trigger function
allows it to be used on line receivers with slow
rise/fall input signals.
All inputs
and
outputs are
equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
®
SOP
TSSOP
ORDER CODES
PACKAGE
T UBE
T & R
SOP
74VHCT132AM
74VHCT132AMTR
TSSOP
74VHCT132ATTR
1/7


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