TMS470MF06607 datasheet(43/65 Pages) TI2

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Address Waitstates

Data Waitstates

RAM

Address Waitstates

Data Waitstates

Flash

0MHz

f(HCLK)

56MHz

28MHz

TMS470MF06607

www.ti.com

SPNS157C

– JANUARY 2012

Table 5-10. Switching Characteristics Over Recommended Operating Conditions for Clocks(1)(2)(3)(4)(5)

PARAMETER

TEST CONDITIONS(6)

MIN

MAX

UNIT

Pipeline mode enabled

f(HCLK)

System clock frequency

MHz

Pipeline mode disabled, 0

flash wait states

System clock frequency Flash

f(PROG/ERASE)

MHz

programming/erase

f(VCLK/VCLK2)

Peripheral VBUS clock frequency

f(HCLK)

MHz

External clock output frequency for

f(ECLK)

MHz

ECP Module

RCLK - Frequency out of PLL macro

180

f(RCLK)

MHz

into R-divider

Pipeline mode enabled

12.50

tc(HCLK)

Cycle time, system clock

Pipeline mode disabled, 0

35.71

flash wait states

Cycle time, system clock - Flash

12.50

tc(PROG/ERASE)

programming/erase

tc(VCLK/VCLK2)

Cycle time, peripheral clock

tc(HCLK)

Cycle time, ECP module external clock

50.0

tc(ECLK)

output

Cycle time, minimum input cycle time

5.56

tc(RCLK)

for the R- divider (RCLK)

(1)

f(HCLK) = f(OSC) / NR *NF /ODPLL/PLLDIV; for details, see the PLL documentation. TI strongly recommends selection of NR and NF

parameters such that NF

≤ 120 and (f(OSC) / NR *NF) ≤ 400.

f(VCLK) = f(HCLK) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the peripheral VBUS clock divider ratio determined by the

VCLKR[3:0] bits in the SYS module.

(2)

Enabling FM mode can reduce maximum rated operating frequencies. The degree of impact is application-specific and the specific

settings, as well as the impact of the settings, should be discussed and agreed upon prior to using FM modes. Use of FM modes do not

impact the maximum rated external clock output, f(ECLK), for the ECP module.

(3)

Pipeline mode enabled or disabled is determined by FRDCNTL[2:0].

(4)

f(ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCTRL.[15:0] register bits in the ECP

module.

(5)

ECLK output will increase radiated emissions within the system that is used. Rated emissions at the device level do not include

emissions due to ECLK output.

(6)

All test conditions assume FM Mode disabled and RAM ECC enabled with 0 waitstates for RAM.

Figure 5-8. Timing - Wait States

NOTE

If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the

maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not

exceeded. The speed of the device clocks may need be derated to accommodate the

modulation depth when FMzPLL frequency modulation is enabled.

Peripheral Information and Electrical Specifications

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