27 / 48 page
IP1001 LF
Data Sheet
27/48
Dec. 18, 2007
Copyright © 2006, IC Plus Corp.
IP1001-DS-R06
4.1
Control Register (Reg0)
Bit
Name
Description
Type
HW
Reset
SW
Reset
0.5:0
Reserved
RO
Always 0
0.6
0.13
1
1
Reserved
1
0
1000Mb/s
0
1
100Mb/s
0.6
Speed Selection
(MSB)
0
0
10Mb/s
R/W
1
NA
0.7
Collision Test
1: Enable COL signal test
0: Disable COL signal test
R/W
0
0
0.8
Duplex Mode
1: Full duplex
0: Half duplex
R/W
1
NA
0.9
Restart Auto-NEG
1: Restart Auto-Negotiation Process
0: Normal operation
R/W
SC
0
SC
0.10
Isolate
1: Isolate PHY from MII, GMII, or RGMII
electrically
0: normal operation
R/W
0
0
0.11
Power Down
1: Power down
0: Normal operation
R/W
0
0
0.12
Auto-Negotiation
Enable
1: Enable Auto-Negotiation Process
0: Disable Auto-Negotiation Process
R/W
1
NA
0.13
Speed Selection
(LSB)
Please refer to bit 0.6 for detail information
R/W
0
NA
0.14
Loopback
1: Enable loop back mode
0: Disable loop back mode
R/W
0
0
0.15
Software Reset
1: PHY software reset
0: normal operation
R/W
SC
0
0 (SC)
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