IP100A LF
Preliminary Data Sheet
39/97
March. 30, 2007
Copyright © 2004, IC Plus Corp.
IP100A LF-DS-R17
11.2.8 TxFrameControl
Class............................. DMA Data Structures, TFD
Base Address ............... Start of TFD
Address Offset .............. 0x04
Access Mode ................ Read/Write
Width ............................ 32 bits
TxFrameControl contains frame control information for the transmit DMA function and the transmit function.
BIT
BIT NAME
BIT DESCRIPTION
1..0
WordAlign
Word Alignment. WordAlign determine the boundary to which transmit
frame lengths are rounded up in the transmit FIFO, and transmitted onto
the network medium.
BIT 1
BIT 0
ALIGNMENT
0
0
Align to Double Word
1
0
Align t o Word
x
1
Alignment Disabled
When using word alignment, it is the responsibility of the host system to
recognize that any added bytes necessary to achieve the desired
alignment may affect byte oriented functions and fields (i.e. if the Ethernet
Length/Type field holds a frame length, this value is not updated to reflect
any bytes added via word alignment).
9..2
FrameId
Frame Identification. FrameId can be used as a frame ID or sequence
number and can be used by the host system (via the TxStatus register) to
determine frames which experienced errors.
12..10
Reserved
Reserved for future use.
13
FcsAppendDisable
FCS Append Disable. If FcsAppendDisable is a logic 1, the IP100A LF
will not append the 4-byte FCS to the end of each transmit frame. In this
case, the host system must supply the frame’s FCS as part of the data
transferred via transmit DMA. An exception exists when a transmit under
run occurs; in this case a guaranteed-bad FCS will be appended to the
frame by the IP100A LF. When FcsAppendDisable is a logic 0, the
IP100A LF will compute and append FCS for each transmit frame.
14
Reserved
Reserved for future use.
15
TxIndicate
Transmit Indicate. If TxIndicate is a logic 1, the IP100A LF will issue a
TxComplete interrupt when transmission of the frame completes.
16
TxDMAComplete
Transmit DMA Complete. When TxDMAComplete is a logic 1, the frame
transfer by transmit DMA is complete. The IP100A LF sets
TxDMAComplete to a logic 1 after completing transfer via transmit DMA,
all fragments specified in the TFD.
30..17
Reserved
Reserved for future use.
31
TxDMAIndicate
Transmit DMA Indicate. If TxDMAIndicate is a logic 1, the IP100A LF will
issue a TxDMAComplete interrupt upon completion of transmit DMA for
this frame. The TFC is read twice by the IP100A LF; the first time to write
the TFC to the transmit FIFO before frame data transfer, and again after
the transmit DMA operation is complete to test TxDMAIndicate in order to
determine whether to generate an interrupt. This dual read process
allows the host system time to change TxDMAIndicate while the transmit
DMA transfer is in progress.
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