IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
61/111
Mar 09, 2007
Copyright © 2004, IC Plus Corp.
IP175C/IP175CH-DS-R14
MII register 1 of PHY0~4 (Each PHY has its own MII register 1 with different PHY address)
PHY
MII
ROM
R/W
Description
Default
Status register
4~0
1.2
--
RO
LL
Link Status
1 = Link Pass
0 = Link Fail
When read as logic 1, indicates that IP175C/IP175CH has
determined a valid link has been established. When read as
logic 0, indicates the link is not valid. This bit is cleared until a
valid link has been established and before reading the contents
of this registers.
0
4~0
1.1
--
Jabber Detect
1 = jabber condition detected
0 = no jabber condition detected
When read as logic 1, indicates that IP175C/IP175CH has
detected a jabber condition. This bit is always 0 for 100Mbps
operation and is cleared after IP175C/IP175CH reset. When
the duration of TXEN exceeds the jabber timer (21ms), the
transmission and loop back functions will be disabled and the
COL is active. After TXEN goes low for more than 500 ms, the
transmitter will be re-enabled.
0
4~0
1.0
--
RO
Extended capability
1 = Extended register capabilities
0 = No extended register capabilities
IP175C/IP175CH has extended register capabilities.
1
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
