IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
59/111
Mar 09, 2007
Copyright © 2004, IC Plus Corp.
IP175C/IP175CH-DS-R14
Register descriptions
R/W = Read/Write,
SC = Self-Clearing,
RO = Read Only,
LL = Latching Low,
LH = Latching High
MII register 0 of PHY0~4 (Each PHY has its own MII register 0 with different PHY address)
PHY
MII
ROM
R/W
Description
Default
Control register
4~0
0.15
--
RW/
SC
Reset
The PHY is reset if user write “1” to this bit. The reset period is
around 2ms. User has to wait for at least 2ms to access
IP175C/IP175CH.
0
4~0
0.14
--
R/W Loop back
1 = Loop back mode
0 = normal operation
When this bit set, IP175C/IP175CH will be isolated from the
network media, that is, the assertion of TXEN at the MII will not
transmit data on the network. All MII transmission data will be
returned to MII receive data path in response to the assertion
of TXEN.
Bit 0.12 is cleared automatically, if this bit is set. User has to
program bit 0.12 again after loop back test.
0
4~0
0.13
--
RW Speed Selection
1 = 100Mbps
0 = 10Mbps
It is valid only if bit 0.12 is set to be 0.
1
4~0
0.12
--
RW Auto-Negotiation Enable
1 = Auto-Negotiation Enable
0 = Auto-Negotiation Disable
1
4~0
0.11
--
R/W Power Down
1: power down mode
0: normal operation
0
4~0
0.10
--
Isolate
IP175C/IP175CH doesn’t support this function.
0
4~0
0.9
--
RW
SC
Restart Auto- Negotiation
1 = re-starting Auto-Negotiation
0 = Auto-Negotiation re-start complete
Setting this bit to logic high will cause IP175C/IP175CH to
restart an Auto-Negotiation cycle, but depending on the value
of bit 0.12 (Auto-Negotiation Enable). If bit 0.12 is cleared then
this bit has no effect, and it is Read Only. This bit is
self-clearing after Auto-Negotiation process is completed.
0
4~0
0.8
--
R/W Duplex mode
1 = full duplex
0 = half duplex
It is valid only if bit 0.12 is set to be 0.
0
4~0
0.7
--
R/W Collision test
0
4~0
0[6:0]
--
RO
Reserved
0
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