TPS2104, TPS2105

VAUX POWER-DISTRIBUTION SWITCHES

SLVS235A – SEPTEMBER 1999 – REVISED APRIL 2000

4

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NO.

DESCRIPTION

NAME

TPS2104

TPS2105

I/O

DESCRIPTION

DBV

D

DBV

D

EN

1

3

I

Active-high enable for IN1-OUT switch

EN

1

3

I

Active-low enable for IN1-OUT switch

GND

2

2

2

2

I

Ground

IN1†

5

5

5

5

I

Main input voltage, NMOS drain (250 m

Ω), require 0.22 µF bypass

IN2†

3

1

3

1

I

Auxilliary input voltage, PMOS drain (1.3

Ω

), require 0.22 µF bypass

OUT

4

7, 8

4

7, 8

O

Power switch output

NC

4, 6

4, 6

No connection

† Unused INx should not be grounded.

detailed description

power switches

n-channel MOSFET

The IN1-OUT n-channel MOSFET power switch has a typical on-resistance of 250 m

Ω at 5-V input voltage, and

is configured as a high-side switch.

p-channel MOSFET

The IN2-OUT p-channel MOSFET power switch has a typical on-resistance of 1.3

Ω at 5-V input voltage and

is configured as a high-side switch. When operating, the p-channel MOSFET quiescent current is reduced to

typically 0.75

µA.

charge pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate

of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires

very little supply current.

driver

The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. To limit large current surges

and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that

controls the rise times and fall times of the output voltage.

enable

The logic enable will turn on the IN2-OUT power switch when a logic high is present on EN (TPS2104) or logic

low is present on EN (TPS2105). A logic low input on EN (TPS2104) or logic high on EN (TPS2105) restores

bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible

with both TTL and CMOS logic levels.