ADC14C080

SNAS375C – SEPTEMBER 2006 – REVISED APRIL 2013

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ADC14C080 Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF

= +1.2V, fCLK = 80 MHz, 50% Duty Cycle, DCS Disabled, VCM = VCMO, CL = 5 pF/pin. Typical values are for TA = 25°C.

Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C

(1) (2)

Units

Parameter

Test Conditions

Typical(3)

Limits

(Limits)

DIGITAL INPUT CHARACTERISTICS (CLK, PD)

VIN(1)

Logical “1” Input Voltage

VD = 3.6V

2.0

V (min)

VIN(0)

Logical “0” Input Voltage

VD = 3.0V

0.8

V (max)

IIN(1)

Logical “1” Input Current

VIN = 3.3V

10

µA

IIN(0)

Logical “0” Input Current

VIN = 0V

−10

µA

CIN

Digital Input Capacitance

5

pF

DIGITAL OUTPUT CHARACTERISTICS (D0–D13, DRDY)

VOUT(1)

Logical “1” Output Voltage

IOUT = −0.5 mA , VDR = 2.4V

2.0

V (min)

VOUT(0)

Logical “0” Output Voltage

IOUT = 1.6 mA, VDR = 2.4V

0.4

V (max)

+ISC

Output Short Circuit Source Current

VOUT = 0V

−10

mA

−ISC

Output Short Circuit Sink Current

VOUT = VDR

10

mA

COUT

Digital Output Capacitance

5

pF

POWER SUPPLY CHARACTERISTICS

IA

Analog Supply Current

Full Operation

100

123

mA (max)

IDR

Digital Output Supply Current

Full Operation(4)

14

mA

Power Consumption

Excludes IDR

(4)

300

369

mW (max)

Power Down Power Consumption

Clock disabled

7

mW

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4 of the Absolute Maximum Ratings Table. However, errors in the A/D conversion can occur if the input goes

above 2.6V or below GND as described in the Operating Ratings section. See Figure 2.

(2)

With a full scale differential input of 2VP-P , the 14-bit LSB is 122.1 µV.

(3)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(4)

IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C13 x

f13) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at

which that pin is toggling.

8

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