6.4 Operating Performance Points

This section describes maximum operating conditions of the device in Table 6-1 and describes each Operating

Performance Point (OPP) for processor clocks and device core clocks in Table 6-2.

Table 6-1. Device Speed Grades

Speed

Grade

VDD_CORE

(V)(1)

MAXIMUM OPERATING FREQUENCY (MHz)

MAXIMUM

TRANSITION

RATE (MT/s)

A53SS

(Cortex-

A53x)

GPU

PRU

Main

Infra

(CBA)

MCUSS

(Cortex-

M4F)

Device/

Power

Manager

(Cortex-

R5F)

SMS

Subsystem

(Dual

Cortex-M4F)

OCSRAM

LPDDR4

T

0.75/0.85

1250

500

333

250

400

400

400

400

1600

0.85

1400

(1)

Nominal operating voltage, see Recommended Operating Conditions.

Table 6-2. Device Operating Performance Points

OPP

A53SS(1)

FIXED OPERATING FREQUENCY OPTIONS (MHz)(2)

MT/s

GPU

PRU

MAIN

INFRA (CBA)

MCUSS

DEVICE/

POWER

MANAGER

SMS /

SMS CBA

OCSRAM

LPDDR4

 

High

 

From

ARM0

PLL

Bypass

to

Speed

Grade

Maximum

500

333,

250,

or

200

250

400

or

200

400

400

400

From

DDR

PLL

Bypass(3)

to

1600

Low

N/A

125

133

133

133

(1)

Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.

(2)

Fixed operating frequency, set by software at boot.

(3)

The DDR PLL output, which sources DDR0_CK0 and DDR0_CK0_n, is typically defined in units of frequency. So the "DDR PLL

Bypass" transaction rate is equal to 2x the DDR PLL output frequency when operating in bypass mode.

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AM625SIP

SPRSP98A – NOVEMBER 2023 – REVISED JUNE 2024

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