2

Functional Diagram

Logic Diagram

TRUTH TABLE

OPERATING MODE

INPUTS

OUPUTS

CP

EDn

Qn

Load “1”

↑

lh

H

Load “0”

↑

ll

L

Hold (Do Nothing)

↑

h

X

No Change

X

H

X

No Change

H = High Voltage Level Steady State.

h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition.

L = Low Voltage Level Steady State.

l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition.

X = Don’t Care.

↑ = Low to High Clock Transition.

2

5

6

9

15

19

16

12

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CP

E

11

1

GND = 10

VCC = 20

3

4

7

8

14

18

17

13

D0

D1

D2

D3

D4

D5

D6

D7

E

D0

D1

D2

D3

D6

D7

Q

D

CP

CP

Q0

Q1

Q2

Q3

Q6

Q7

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q4

Q5

D4

D5

CD54HC377, CD74HC377, CD54HCT377, CD74HCT377