TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

22

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz

sixteen times (16

×) the baud rate. The formula for the divisor is:

divisor # = CLK frequency input

÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must

be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either

of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. For

baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy of the selected

baud rate is dependent on the selected crystal frequency.

receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register and an RBR. Timing is supplied by the 16

× receiver

clock (RCLK). Receiver section control is a function of the ACE line control register.

The ACE receiver shift register receives serial data from the serial input (SIN) terminal. The receiver shift

register then converts the data to a parallel form and loads it into the RBR. When a character is placed in the

RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared

when the data is read out of the RBR.

scratch register

The scratch register is an 8-bit register that is intended for programmer use as a scratchpad, in the sense that

it temporarily holds programmer data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register. Timing is supplied by the baud

out (BAUDOUT) clock signal. Transmitter section control is a function of the ACE line control register.

The ACE THR receives data off of the internal data bus and, when the shift register is idle, moves it into the

transmitter shift register. The transmitter shift register serializes the data and outputs it at the serial output

(SOUT). When the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an

interrupt is generated. This interrupt is cleared when a character is loaded into the register.