t

rCL

t

BUF

t

LOW

t

fCL

t

HD; STA

t

SP

t

rCL1

t

HD; STA

t

SU; STA

t

HD; DAT

t

SU; DAT

t

HIGH

t

SU; STO

SCL

SDA

t

fDA

t

rDA

Repeated Start

Stop

Start

Power-On Sequence Timing

V

DD

100% V

DD

~ 0.9 V

t

0

1

≥

0 V

~ 0.9 V

0 V

~ 0.9 V

0 V

SCL

SDA

SCL High

SDA Low

I C Bus Activity

2

I C

2

Bus Activity

100% V

I2C

100% V

I2C

TSC2003-Q1

www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

Figure 1. Timing Diagram

During TSC2003 power-up, the I2C bus should be idle. In other words, the SDA and SCL lines must be high

before the TSC2003 supply (VDD) ramps up greater than 0.9 V. If the TSC2003 uses the same supply as the I

2C

bus pullup resistors (VI2C), then a 1-µF capacitor placed very close to the TSC2003 supply pin causes the

TSC2003 supply to ramp up more slowly (see Figure 2). If the TSC2003 supply (VDD) is different than the supply

to the I2C bus pullup resistors (VI2C), then VI2C should be turned on before the TSC2003 supply (VDD) is powered

up.

Figure 2. Power-On Sequence Timing Diagram

Copyright © 2008, Texas Instruments Incorporated

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Product Folder Link(s): TSC2003-Q1