7 Detailed Description

7.1 Overview

The ’HC367, ’HCT367, ’HC368, and CD74HCT368 silicon gate CMOS three-state buffers are general purpose

high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed

operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS

circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up

to 15 low power Schottky inputs.

The ’HC367 and ’HCT367 are non-inverting buffers, whereas the ’HC368 and CD74HCT368 are inverting

buffers. These devices have two output enables, one enable (OE1) controls 4 gates and the other (OE2) controls

the remaining 2 gates.

The ’HCT367 and CD74HCT368 logic families are speed, function and pin compatible with the standard LS logic

family.

7.2 Functional Block Diagram

1OE

1

1A1

2

1Y1

3

2OE

15

2A1

12

2Y1

11

1A2

4

1Y2

5

1A3

6

1Y3

7

1A4

9

1Y4

10

2A2

14

2Y2

13

7.3 Device Functional Modes

Table 7-1. Truth Table(1)

INPUTS

OUTPUTS (Y)

OE

A

HC/HCT367

HC/HCT368

L

L

L

H

L

H

H

L

H

X

(Z)

(Z)

(1)

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,

Z = High Impedance (OFF) State

CD54HC367, CD74HC367, CD54HCT367

CD74HCT367, CD54HC368, CD74HC368, CD74HCT368

SCHS181E – NOVEMBER 1997 – REVISED FEBRUARY 2022

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