1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VREF

VOUT

AVSS

AVDD

AGND

DGND

DGND

DGND

DVDD

DGND

CLR

DVDD

DGND

CS

SCLK

SDIN

(TOP VIEW)

DAC8581

SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted).

DAC8581

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

+AVDD

4.0

5

6.0

V

–AVDD

–4.0

–5

–6.0

V

DVDD

1.8

AVDD

V

IDVDD

10

20

μA

IDD

IREF and IDVDD included

17

24

mA

ISS

–23

–32

mA

TEMPERATURE RANGE

Specified performance

–40

+85

°C

PIN CONFIGURATION

PW PACKAGE

TSSOP-16

TERMINAL FUNCTIONS

TERMINAL

NAME

NO.

VREF

1

Reference input voltage.

VOUT

2

DAC output voltage. Output swing is ±VREF

AVSS

3

Negative analog supply voltage, tie to –5 V

AVDD

4

Positive analog supply voltage, tie to +5 V

AGND

5

The ground reference point of all analog circuitry of the device. Tie to 0 V.

DGND

6, 7, 8, 15

Tie to DGND to ensure correct operation.

SDIN

9

Digital input, serial data. Ignored when CS is high.

SCLK

10

Digital input, serial bit clock. Ignored when CS is high.

Digital input. Chip Select (CS) signal. Active low. When CS is high, SCLK and SDI are ignored. When CS is low,

CS

11

data can be transferred into the device.

DGND

12

Ground reference for digital circuitry. Tie to 0 V.

DVDD

13

Positive digital supply, 1.8 V–5.5 V compatible

Digital input for forcing the output to midscale. Active low. When pin CLR is low during 16th SCLK following the

falling edge of CS, the falling edge of 16th SCLK sets DAC Latch to midcode, and the DAC output to 0 V. When

CLR

14

pin CLR is High, the falling edge of 16th SCLK updates DAC latch with the value of input shift register, and

changes DAC output to corresponding level.

DVDD

16

Tie to DVDD to ensure correct operation.

4

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