DP83849CVSSLASHNOPB datasheet(69/100 Pages) TI2

69 / 100 page

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7.2.8 CD Test and BIST Extensions Register (CDCTRL1)

This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control

and status for the packet BIST function.

7.2.9 Phy Control Register 2 (PHYCR2)

This register provides additional general control.

Table 40. CD Test and BIST Extensions Register (CDCTRL1), address 1Bh

Bit

Bit Name

Default

Description

15:8

BIST_ERROR_COUNT

0, RO

BIST ERROR Counter:

Counts number of errored data nibbles during Packet BIST. This

value will reset when Packet BIST is restarted. The counter sticks

when it reaches its max count.

7:6

RESERVED

0, RW

RESERVED:

Must be zero.

BIST_CONT_MODE

0, RW

Packet BIST Continuous Mode:

Allows continuous pseudo random data transmission without any

break in transmission. This can be used for transmit VOD testing.

This is used in conjunction with the BIST controls in the PHYCR

abled, bit 0 of the 10BTSCR (1Ah), JABBER_DIS = 1.

CDPATTEN_10

0, RW

CD Pattern Enable for 10Mb:

1 = Enabled.

0 = Disabled.

RESERVED

0, RW

RESERVED:

Must be zero.

10MEG_PATT_GAP

0, RW

Defines gap between data or NLP test sequences:

1 = 15

µs.

0 = 10

µs.

1:0

CDPATTSEL[1:0]

00, RW

CD Pattern Select[1:0]:

If CDPATTEN_10 = 1:

00 = Data, EOP0 sequence

01 = Data, EOP1 sequence

10 = NLPs

11 = Constant Manchester 1s (10MHz sine wave) for harmonic dis-

tortion testing.

Table 41. Phy Control Register 2 (PHYCR2), address 1Ch

Bit

Bit Name

Default

Description

15:10

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

SOFT_RESET

0, RW/SC

Soft Reset:

Resets the entire device minus the registers - all configuration is

preserved.

1= Reset, self-clearing.

8:0

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

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