TAS3103A datasheet(17/152 Pages) TI

17 / 152 page

1−9

1.7

Operational Modes

The TAS3103A operation is governed by I/O terminal voltage level settings and register/coefficient settings within the

TAS3103A. The terminal settings are wholly sufficient to address all external environments, allowing the remaining

configuration settings to be determined by either I2C commands or by the content of an I2C serial EEPROM (when

the I2C master mode is selected).

1.7.1

Terminal-Controlled Modes

1.7.1.1 Clock Control

PLL1

PLL0

DAP CLOCK

× MCLK

(11

× MCLK)/2 (default)

(11

× MCLK)/4

MCLK (PLL bypass)

MICROCLK_DIV

MICROPROCESSOR CLOCK

DAP clock/4 (default)

DAP clock

XTALI

MCLKI

Reference

Divider

PLL

PLL0

Digital

Audio Processor

(DAP) Clock

MICROCLK_DIV

MCLK

PLL1

÷ 11

Microprocessor

Clock < 36 MHz

Microprocessor

Scaler

1400

y Fs 3 DAP Clock 3 136 MHz

y 11

1.7.1.2 I2C Bus Setup

SLAVE ADDRESS

CS1

CS0

0x68/69 (default)

0x6A/6B

0x6C/6D

0x6E/6F

I2CM_S

I2C BUS MODE

Slave

Master (default)—EEPROM device ID = 0xA0

TAS3103A 데이터시트(PDF) 17 Page - Texas Instruments

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