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ISO7340C 데이터시트(PDF) 20 Page - Texas Instruments

부품명 ISO7340C
상세설명  ISO734x Robust EMC, Low-Power, Quad-Channel Digital Isolators
PDF  38 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

ISO7340C 데이터시트(HTML) 20 Page - Texas Instruments

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ISO7340C, ISO7340FC, ISO7341C, ISO7341FC, ISO7342C, ISO7342FC
SLLSEI6G – SEPTEMBER 2014 – REVISED JANUARY 2017
www.ti.com
Product Folder Links: ISO7340C ISO7340FC ISO7341C ISO7341FC ISO7342C ISO7342FC
Submit Documentation Feedback
Copyright © 2014–2017, Texas Instruments Incorporated
(1)
See the Safety-Related Certifications section for detailed isolation ratings.
9.3 Feature Description
The ISO734x family of devices are available in multiple channel configurations and default output state options to
enable wide variety of application uses.
PART NUMBER
CHANNEL DIRECTION
RATED ISOLATION
MAXIMUM DATA RATE
DEFAULT OUTPUT
ISO7340C
4 Forward,
0 Reverse
3000 VRMS / 4242 VPK
(1)
25 Mbps
High
ISO7340FC
Low
ISO7341C
3 Forward,
1 Reverse
High
ISO7341FC
Low
ISO7342C
2 Forward,
2 Reverse
High
ISO7342FC
Low
9.3.1 Electromagnetic Compatibility (EMC) Considerations
Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge
(ESD), electrical fast transient (EFT), surge, and electromagnetic emissions. These electromagnetic disturbances
are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level
performance and reliability depends, to a large extent, on the application board design and layout, the ISO734x
family of devices incorporates many chip-level design improvements for overall system robustness. Some of
these improvements include:
•
Robust ESD protection cells for input and output signal pins and inter-chip bond pads.
•
Low-resistance connectivity of ESD cells to supply and ground pins.
•
Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.
•
Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance
path.
•
PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic
SCRs.
•
Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.



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