5.8 Switching Characteristics

over recommended operating conditions unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

See Figure 6-5

1

1.5

2.4

ns

tPHL

Propagation delay time, high-to-low-level output

1

1.5

2.4

ns

tr

Differential output signal rise time

1

1.9

ns

tf

Differential output signal fall time

1

1.9

ns

tsk(o)

Output skew(2)

100

ps

tsk(p)

Pulse skew (|tpHL - tpLH|)

22

100

ps

tsk(pp)

Part-to-part skew(3)

600

ps

tjit(per)

Period jitter, rms (1 standard deviation)(4)

All inputs 100 MHz clock input

0.2

1

ps

tjit(c-c)

Cycle-to-cycle jitter(4)

All inputs 100 MHz clock input

5

36

ps

tjit(pp)

Peak-to-peak jitter(4) (5)

All inputs 200 Mbps 215-1 PRBS input

46

158

ps

tPZH

Enable time, high-impedance-to-high-level output

See Figure 6-6

9

ns

tPZL

Enable time, high-impedance-to-low-level output

9

ns

tPHZ

Disable time, high-level-to-high-impedance output

See Figure 6-6

10

ns

tPLZ

Disable time, low-level-to-high-impedance output

10

ns

(1)

All typical values are at 25°C and with a 3.3V supply voltage.

(2)

tsk(o), output skew is the magnitude of the time difference in propagation delay times between any specified terminals of a device.

(3)

tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

(4)

Stimulus jitter has been subtracted from the measurements.

(5)

Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)).

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SN65MLVD047A

SLLS736B – JULY 2006 – REVISED MARCH 2024

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