THS7347

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SLOS531B

– MAY 2007 – REVISED OCTOBER 2011

READING FROM THE THS7347

The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master

initiates a write operation to the THS7347 by generating a start condition (S) followed by the THS7347 I2C

address, in MSB-first order, followed by a '0' to indicate a write cycle. After receiving an acknowledge from the

THS7347, the master presents the subaddress (channel) of the register it wants to read. After the cycle is

acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).

The second phase is the data phase. In this phase, an I2C master initiates a read operation to the THS7347 by

generating a start condition followed by the THS7347 I2C address, in MSB-first order, followed by a '1' to indicate

a read cycle. After an acknowledge from the THS7347, the I2C master receives one byte of data from the

THS7347. After the data byte has been transferred from the THS7347 to the master, the master generates a

not-acknowledge (A) followed by a stop. As with the Write function, to read all channels, steps 1 through 11 must

be repeated for each channel desired.

THS7347 Read Phase 1:

Step 1

0

I2C Start (Master)

S

Step 2

7

6

5

4

3

2

1

0

I2C General Address (Master)

0

1

0

1

1

X

X

0

Where each X logic state is defined by I2C-A1 and I2C-A0 pins being tied to either VDD or GND.

Step 3

9

I2C Acknowledge (Slave)

A

Step 4

7

6

5

4

3

2

1

0

I2C Read Channel Address (Master)

0

0

0

0

0

Addr

Addr

Addr

Where Addr is determined by the values shown in Table 2.

Step 5

9

I2C Acknowledge (Slave)

A

Step 6

0

I2C Start (Master)

P

Copyright

© 2007–2011, Texas Instruments Incorporated

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