Initialize

Initialize

DATA IN Can be Tied or Held High

1

2

3

5

4

6

10

11

12

16

MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

MSB–8 MSB–9 LSB+1

8

7

9

MSB–6 MSB–7

Previous Conversion Data

MSB

EOC

LSB

DATA OUT

I/O CLOCK

DATA IN

CS

D7

MSB

1

Hi-Z State

A/D Conversion Interval

t

conv

Access Cycle

Sample Cycle

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

Channel Address

Output Data

Format

Pad

Zeros

1

2

3

5

4

6

10

11

12

16

MSB–1 MSB–2 MSB–3 MSB–4 MSB–5

MSB–8 MSB–9 LSB+1

D6

D5

D4

D3

D2

D1

D0

D7

8

7

9

MSB–6 MSB–7

Previous Conversion Data

MSB

EOC

Initialize

INT

LSB

DATA OUT

I/O CLOCK

DATA IN

CS

D7

MSB

1

Hi-Z State

A/D Conversion Interval

Initialize

t

conv

Access Cycle

Sample Cycle

Shift in New Multiplexer Address,

Simultaneously Shift Out Previous Conversion Result

Channel Address

Output Data

Format

Pad

Zeros

TLV2556

www.ti.com

SLAS355B – DECEMBER 2001 – REVISED DECEMBER 2015

NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a set-up time after the CS falling edge before

responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 7. Timing for 16-Clock Transfer Using CS With DATA OUT Set for MSB First

NOTE: To minimize errors caused by noise at CS, the internal circuitry waits for a set-up time after the CS falling edge before

responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 8. Timing for Default Mode Using CS: (16-Clock Transfer, MSB First, Ext. Ref, Pin 19 = EOC,

Input = AIN0)

Copyright © 2001–2015, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Links: TLV2556