NB679A

–28V VIN, FIXED 5.1V-8A BUCK CONVERTER WITH LDO AND LP# VOUT SCALING

NB679A Rev. 1.03

www.MonolithicPower.com

17

7/27/2017

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The inductance value can be calculated with

Equation (11):

OUT

OUT

SW

L

IN

VV

L

(1

)

F

I

V



 



(11)

Where ΔI

L is the peak-to-peak inductor ripple

current.

The inductor should not saturate under the

maximum inductor peak current (including short

current), so it is suggested to choose Isat > 11A.

PCB LAYOUT GUIDELINES

Efficient PCB layout is critical for optimum IC

performance. For best results, refer to Figure 6

and follow the guidelines below. For more

information, refer to AN087.

1. Place the high current paths (GND, IN, and

SW) very close to the device with short, direct,

and wide traces.

2. Place the input capacitors as close to IN and

GND as possible.

3. Place the decoupling capacitor as close to

VCC

and GND

as possible.

Keep the

switching node (SW) short and away from the

feedback network.

4. Keep the BST voltage path as short as

possible with a > 25 mil trace.

5. Keep the IN and GND pads connected with a

large copper plane to achieve better thermal

performance. Add several vias with a 10 mil

drill/18mil copper width close to the IN and

GND pads to help thermal dissipation.

6. Keep the Vout sense trace over 20 mil.

7. A 4-layer layout is strongly recommended to

achieve better thermal performance.

VIN

SW

VOUT

PGND

VOUT

3

4

5

6

VCC

AGND

LDO

PGND

BST

SW

VOUT

Vin

1

8

12

11

10

9

2

7

LP#

PG

NS

EN

Vout

PG

L

7mm*6.6mm

0805

0603

0402

Vout

Figure 6: Recommend PCB Layout