IP5328P

V1.2

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Copyright © 2015, Injoinic Corp.

7. PCB Layout

Here below lists essential precautions that may affect the function and performance on PCB layout, more

details will be attached in another document if any.

Location of VSYS capacitor

Both power and current is large under normal operating, location of capacitor on VSYS net affects the

stability of DCDC. VSYS capacitor should be placed as close to VSYS pin and EPAD as possible, deploy large copper

pour and add more vias, decrease the area of current loop between capacitor and IC and reduce the parasitic

parameter.

VSYS pin distribute at two sides of the IC, capacitor should be placed on each side and connect the two pins

with wide (wider than 100mil) copper on PCB board.

10mOhm sample resistor

IP5328P sample the current on 10mOhm between VSN and VSP pin to take control of input charging current,

output overcurrent protection, output light load power down. VSN and VSP tracks should keep away from signals

that may generate large interference, lay to the 10mOhm resistor separately, do not overlay with other current

track or VSYS track. Though VSP and VSYS are same net on PCB, layout of those two pins should be separated.

To enhance the immunity of interference of sample signal, 100nF filter capacitor are needed on VSN and VSP

pins and place as close as possible.

The layout is illustrated below: